a. Field of the Invention
The present invention pertains generally to partitioning of data streams and more specifically for programmable logic circuits for the detection of page boundaries in data streams.
b. Description of the Background
Page boundaries are used during data transfer for various purposes. In some cases, a page boundary may indicate a physical limitation of data storage. In other cases, long streams of data may be broken up into smaller sections for the calculation of CRC, parity, or other data integrity mechanisms.
In many cases, various embodiments are implemented in hardware, using a counter register or other preconfigured logic circuitry. Such circuitry may be dedicated to the performance of a single task and thereby be optimized for speed.
However, pagination circuitry, such as described above may require rather complex counter registers that increment with every clock cycle or every transfer of data. Counter registers may also occupy a relatively large area of an integrated circuit, which is space that may be otherwise used for additional circuitry. Further, as clock speeds increase, it has become increasingly difficult to design counter register circuits that are capable of counting at higher and higher speeds.
It would therefore be advantageous to provide a method and circuit for detecting page boundaries that uses a small amount of integrated circuit space. Further, it would be advantageous to provide a method and circuit that are capable of performing the required tasks at a very high speed.